此領域的工作機會 請點我

(From 104人力銀行,以Nvidia研發替代役為例,有1/3的工作職缺與測試領域相關)


VLSI Test Technology Workshop 2018

Contact: [TOP OF THE PAGE]

Office Rm. F5028, Department of Computer Science and Engineering
National Sun Yat-sen University, 804, Kaohsiung
Phone Office +886-75252000 ext.4320
Lab +886-79765846
Cell Phone +886-972590908
Fax +886-75254301
實驗室方向簡介 Past, Present and Future of Test
smli@cse.nsysu.edu.tw
a0950095@g-mail.nsysu.edu.tw
likathy42@gmail.com
katherineshuminli@gmail.com
kath.li.888@gmail.com

Announcement: [TOP OF THE PAGE]

2018 恭賀!! 李淑敏教授指導博士班學生李建德榮獲【2018 IEEE Asian Test Symposium】論文接受
恭賀!! 李淑敏教授指導學生江勖豪榮獲【2018 IEEE International Test Conference in Asia】論文接受
恭賀!!李淑敏教授指導學生吳佳霖榮獲【2018 IEEE International Symposium on VLSI Design, Automation and Test】論文接受
2017 恭賀!! 李淑敏教授指導學生陳信志、侯博鈞,鄧人豪教授指導學生劉濱翰、劉芸瑄、黃唯豪、陳仕賢,榮獲2017跨領域工程專題競賽與成果展 - 課程組【佳作】
2016 國立台灣大學電機工程系 張耀文老師
研究生學習秘笈之快快樂樂做研究 請點我
恭賀!!博士班學生李建德榮獲【2016年雲端計算與大數據研討會最佳論文獎】
恭賀!!李淑敏教授榮獲【2016 IEEE Education Society Mac E. VanValkenburg Award】
國際合作上海復旦大學教授吳永輝教授來台研究
蒞臨本實驗室沈浸台灣八景之一,著作成果斐然 請點我
指導學生:李建德、侯博鈞、楊家豪、陳信志,參加經濟部技術處主辦「2015大專院校專利分析與布局競賽」獲得【潛力獎】
2015 恭賀!!碩一學生李建德榮獲【2016 IEEE VLSI Test Symposium】論文接受
恭賀!!碩一學生李建德榮獲【2016 IEEE Asia and South Pacific Design Automation Conference 】論文接受
恭賀!! 李淑敏老師榮升中山大學教授
2014 指導學生:蔡耀宇、林曉慶、李沿槱,參加經濟部技術處主辦「2014大專院校專利分析與布局競賽」獲得【入圍獎】
恭賀!!李淑敏副教授榮升IEEE資深會員【IEEE Senior Member】
2013 恭賀!!李淑敏副教授於【2013大專院校專利分析與布局競賽
擔任【EDA&T】隊伍之指導老師
榮獲【潛力獎】
恭賀!! 李淑敏副教授於【教育部顧問室資訊軟體人才培育先導計畫】
擔任【2013年第23次ITSA線上程式設計大賽】指導老師
榮獲【績優】團隊
恭賀!! 李淑敏副教授於【 教育部顧問室資訊軟體人才培育先導計畫】
擔任【 2013 年第 24 次 ITSA 線上程式設計大賽】指導老師
榮獲【績優】團隊
恭賀!! 李淑敏副教授於【 教育部顧問室資訊軟體人才培育先導計畫】
擔任【 2013 年第 25 次 ITSA 線上程式設計大賽】指導老師
榮獲【績優】團隊
恭賀!! 李淑敏副教授申請的大專生國科會計畫通過
恭賀!! 李淑敏副教授指導學生程柏銓同學、郭可驥副教授指導學生許訓嘉同學、與電機系辜德典同學和陳致霖同學參加100 學年度大校院智慧電子系統(IE)設計競賽 - 核心技術組 【優等】
2012 恭賀!! 李淑敏老師榮升中山大學副教授
2011 恭賀!! 李淑敏教授指導大學部學生:蔣孟剛、劉家倫、李育賢,參加教育部主辦「99學年度大學校院積體電路電腦輔助設計(CAD)軟體製作競賽」榮獲定題A組-測試與合成組【佳作】

Education: [TOP OF THE PAGE]

(1) B.S., Dept. of Computer Science, Rutgers, the State University of New Jersey
(新澤西州立羅格斯大學布溪校區資訊科學系).
(2) M.S., Dept. of Computer and Information System, National Chiao Tung University
(交通大學資訊科學研究所).
(3) Ph.D., Dept. of Electronics Engineering, National Chiao Tung University
(交通大學電子工程研究所).

Course: [TOP OF THE PAGE]

● Introduction to EDA&T (Selective Course)
● Advanced VLSI & SoC Testing (Selective Course, English )
● Computer Architecture (Required Course in Graduate School)
● Computer Organization (Required and Selective Course, English)
● SoC Design Flow & Tools (Required Course in Graduate School)
● Design for Manufacturability (Selective Course)
● 高科技專利 (Selective Course)
● Engineering Mathematics for Computer Science (Required Course, English)
● SoC Testing (Graduate Course)
● Calculus II (Required Course)
● IC Lab (Required Course in Graduate School)
● Programing Language (Required Course)
● Kernel-Based Machine learning
● QT and Windows Programming
● Big Data Analysis and Practice

Areas of Interst: [TOP OF THE PAGE]

● Testing and Design for Testability: Test Design, ATPG,BIST and DFT, Core and System Test
● Physical Design/Automatic Placement and Routing (APR) : Floorplanning, Routing
● Signal Intergrity (SI, 訊號整合) and Power Intergrity (PI, 功率整合), Crosstalk-Induced Glitch and Delay (串音所致之突波與延遲)
● Computer Architecture & Organization
● Green Electronics System Design, Smart Electronics System Design, Smart Grid System Design
● Design Verification
● Computer Aided Design (CAD), Electronic Design Automation (EDA), Test Automation
● Modeling and Simulation for Interconnect, System in Package (SiP), and 3D IC: Interconnect modeling, Design for Manufacturability, Yield Optimization, Reliability Analysis, Emerging Technologies
● Power/Energy-Aware Embedded Systems Design
● Algorithm Design & implementation (演算法分析設計與實作)
● Network-On-Chip Program Design (網路晶片程式設計)
● Graph Theory Program Design (圖論程式設計)
● GUI Program Design (圖形介面程式設計)
● Electronic Program Design (電子設計自動化)
● IC Design & Testing (積體電路設計與測試)
● Automatic Placement and Routing (APR, 平面規劃與繞線器設計)
● 3D IC & System-In-Package Design (三維晶片與系統層級封裝設計)
● Cloud Computing (雲端計算), Security of Cloud Computing (雲端計算安全)
● Financial Engineering (財務工程) , High-frequency trading (高頻交易), Automatic Trading (交易自動化), Algorithmic trading (程式交易), Financial 4.0 (金融 4.0)
● Kernel-Based Machine learning (核心基礎的機器學習)
● GUI (Graphical User Interface) and Windows Programming (圖形用戶介面和視窗程式訓練)
● CIM (Computer-Integrated Manufacturing System), Industries 4.0 (工業 4.0)
● MCS/MES (Material Control/Execution System) modeling & optimization; smart manufacturing (智慧製造), Manufacturing Automation (生產自動化))
● Block Chain Technology and Application (區塊鏈基礎研究與應用)
● Intelligent Vehicle (智慧車用電子), Security of Intelligent Vehicle (智慧車用電子安全)
● Time Series Predictor and AI Study (時間序列預測器與人工智慧相關研究)
● Hardware Trojan and Physical Unclonable Function (硬體木馬與物理不可複製函數, 硬體安全設計與測試)
● AI Hardware Acceleration, AI Hardware Parallel Computing
● Automatic Package Router (自動封裝繞線器), Automatic Substrate Router (自動基底層繞線器)
● AI Router (人工智慧實體繞線器)
● Hardware Security (硬體安全)

Related Publications:: [TOP OF THE PAGE]

International Journals International Conferences Domestic Conferences
I. International Journals:
[1] K. S.-M. Li, C. Su, Y.-W. Chang, C.-L. Lee, and J.-E Chen, “IEEE Standard 1500 Compatible Interconnect Diagnosis for Delay and Crosstalk Faults,” IEEE Trans. Computer-Aided Design, Vol. 25, No. 11, pp. 2513-2525, November 2006.
[2] K. S.-M. Li, C.-L. Lee, C. Su, and J.-E Chen, “IEEE Standard 1500 Compatible Oscillation Ring Test Methodology for Interconnect Delay and Crosstalk Detection,” Journal of Electronic Testing: Theory and Applications, Vol. 23, Issue 4, pp. 341-355, August 2007.
[3] K. S.-M. Li, Y.-M. Chang, C.-L. Lee, C. Su, and J.-E Chen, “Multilevel Full-Chip Routing with Testability and Yield Enhancement,” IEEE Trans. on Computer-Aided Design, Vol. 26, Issue. 9, pp. 1625-1636, September 2007.
[4] S.-J. Wang, P-C. Tsai, H.-M. Weng and K. S.-M. Li, “Test Data and Test Time Reduction for LOS Transition Test in Multi-Mode Segmented Scan Architecture,” International Journal of Electrical Engineering, Vol. 15, No. 2, pp.71-78, April 2008.
[5] S.-J. Wang, K.-L. Peng, K.-C. Hsiao and K. S.-M. Li, “Layout-Aware Scan Chain Reorder for Launch-off-Shift Transition Test Coverage,” ACM Trans. on Design Automation of Electronic Systems, Vol. 13, Issue. 4, Article 64, pp.64:1-64:16, September 2008.
[6] K. S.-M. Li, C.-L. Lee, C. Su, and J. E. Chen, “A Unified Detection Scheme for Crosstalk Effects in Interconnection Bus,” IEEE Trans. on Very Large Scale Integration Systems, Vol. 17, Issue. 2, pp.306-311, February 2009.
[7] S.-J. Wang, K. S.-M. Li, S.-C. Chen, H.-Y. Shiu and Y.-L. Chu, “Scan-Chain Partition for High Test-Data Compressibility and Low Shift Power Under Routing Constraint,” IEEE Trans. on Computer-Aided Design, Vol. 28, Issue 5, pp. 716-727, May 2009.
[8] K. S.-M. Li, “Multiple Scan Trees Synthesis for Test Time/Data and Routing Length Reduction Under Output Constraint,” IEEE Trans. on Computer-Aided Design, Vol. 29, Issue. 4, pp. 618-626, April 2010.
[9] K. S.-M. Li and J.-Y. Huang, “Synthesizing Multiple Scan Trees to Optimize Test Application Time,” IEEE Design & Test of Computers, Vol. 28, Issue 2, pp. 62-69, March/April 2011.
[10] K. S.-M. Li, C.-Y. Pai, and L.-B. Chen, “Maximal Interconnect Resilient Methodology for Fault Tolerance, Yield, and Reliability Improvement in Network on Chip,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E94-A, No.12, pp. 2649-2658, December 2011.
[11] K. S.-M. Li and Y.-Y. Liao, “Layout-Aware Multiple Scan Tree Synthesis for 3D SoCs,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 31, No. 12, pp. 1930-1934, December 2012.
[12] K. S.-M. Li, “CusNoC: Fast Full-Chip Custom NoC Generation,” in IEEE Trans. on Very Large Scale Integration Systems, Vol. 21, No. 4, pp. 692-705, April 2013.
[13] K. S.-M. Li and Y.-Y. Liao, “IEEE 1500 Compatible Multilevel Maximal Concurrent Interconnect Test,” in IEEE Trans. on Very Large Scale Integration Systems, Vol. 21, No. 7, pp.1333-1337, July 2013.
[14] K. S.-M. Li, “Oscillation and Transition Tests for Synchronous Sequential Circuits,” IEEE Trans. on Very Large Scale Integration Systems, Vol. 21, Issue 12, pp. 2338-2343, December 2013.
[15] K. S.-M. Li, Y.-C. Ho and L.-B. Chen, “Interconnect-Driven Floorplanning with Noise-Aware Buffer Planning,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E96-A, No. 12, pp. 2467-2474, December 2013.
[16] K.-T. Yang, W.-K. Lai, K. S.-M. Li and Y.-C. Lin, “Event-Based Clustering Architecture for Power Efficiency in Wireless Sensor Networks,” International Journal of Distributed Sensor Networks, Vol. 2014, pp. 1-12, May 2014.
[17] K. S.-M. Li, Y.-C. Ho, Y.-W. Yang and L.-B. Chen, “An Oscillation-Based On-Chip Temperature-Aware Dynamic Voltage and Frequency Scaling Scheme in System-on-a-Chip,” IEICE Transactions on Information and Systems, Vol. E97-D, No. 9, pp. 2320-2329, September 2014.
[18] K. S.-M. Li and S.-J. Wang, “Design Methodology of Fault-Tolerant Custom 3D Network-on-Chip,” ACM Trans. on Design Automation of Electronic Systems, Vol. 22, Issue 4, Article No.63, pp. 63.1-63.20, July 2017.
[19] S.-J. Wang, K.-T. Yeh and K. S.-M. Li, “Exploiting Distribution of Unknown Values in Test Responses to Optimize Test Output Compactors,” Integration, the VLSI Journal, accepted, December 2017.
[20] K. S.-M. Li, S.-J. Wang, R.-T. Gu and B.-C. Cheng, “Layout-Aware Optimized Prebond Silicon Interposer Test Synthesis,” IEEE Design & Test of Computers, Vol. 34, Issue 6, pp. 77-83, 2017.
[21] J.-D. Li, C.-H. Kuo, G.-R. Lu, S.-J. Wang, K. S.-M. Li, T.-Y. Ho, H.-M. Chen and S.-Y. Hu, "Co-Placement Optimization in Sensor-Reusable Cyber-Physical Digital Microfluidic Biochips." Microelectronics Journal, Under Revision.

[BACK TO TOP]
II. International Conferences:
[1] K. S.-M. Li, Y.-H. Cherng and Y.-W. Chang, “Noise-Aware Buffer Planning for Interconnect-Driven Floorplanning,” in Proc. 8th ACM/IEEE Asia South Pacific Design Automation Conf., pp. 423-426, January 2003.
[2] B.-S. Liu, C.-L. Lee, K. S.-M. Li and J.-E Chen, “Crosstalk Fault Testing by Using Oscillation Ring Testing Methodology for SOC Interconnection Lines,” in Proc. IEEE International Test Synthesis Workshop, 2004.
[3] K. S.-M. Li, C.-L. Lee, C. Su and J.-E Chen, “A Unified Approach to Detecting Crosstalk Faults of Interconnects in Deep Sub-micron VLSI,” in Proc. 9th IEEE Asia Test Symposium, pp. 145-150, November 2004.
[4] K. S.-M. Li, C.-L. Lee, C. Su and J.-E Chen, “Oscillation Ring Based Interconnect Test Scheme for SOC,” in Proc. 10th ACM/IEEE Asia South Pacific Design Automation Conf., pp. 184-187, January 2005.
[5] K. S.-M. Li, C.-L. Lee, Y.-W. Chang, C. Su and J.-E Chen, “Multilevel Full-Chip Routing with Testability and Yield Enhancement,” in Proc. 5th ACM/IEEE International Workshop on System Level Interconnect Prediction, pp. 29-36, April 2005.
[6] K. S.-M. Li, C.-L. Lee, C. Su and J.-E Chen, “Finite State Machine Synthesis for At-Speed Oscillation Testability,” in Proc. 14th IEEE Asia Test Symposium, pp. 360-365, December 2005.
[7] K. S.-M. Li, C.-L. Lee, Y.-W. Chang, C. Su and J.-E Chen, “IEEE Standard 1500 Compatible Interconnect Diagnosis for Delay and Crosstalk Faults,” in Proc. 11th ACM/IEEE Asia South Pacific Design Automation Conf., pp. 366-371, January 2006.
[8] K.-L. Peng, S.-J. Wang and K. S.-M. Li, “Layout-Aware Scan Chain Reorder for Skewed-Load Transition Test Coverage,” in Proc. 15th IEEE Asia Test Symposium, pp. 169-174, November 2006.
[9] S.-J. Wang, Y.-T. Chen and K. S.-M. Li, “Low Capture Power Test Generation for Launch-off-Capture Transition Test Based on Don’t-Care Filling,” in Proc. IEEE International Symposium on Circuits and Systems, pp. 3683-3686, May 2007.
[10] X.-L. Li, S.-J. Wang and K. S.-M. Li, “Layout-Aware Multi-Layer Multi-Level Scan Tree Synthesis,” in Proc. 16th IEEE Asian Test Symposium, pp. 129-132, October 2007.
[11] S.-J. Wang, P.-C. Tsai, H.-M. Weng and K. S.-M. Li, “Test Data and Test Time Reduction for LOS Transition Test in Multi-Mode Segmented Scan Architecture,” in Proc. 16th IEEE Asian Test Symposium, pp. 95-98, October 2007.
[12] S.-J. Wang, S.-C. Chen and K. S.-M. Li, “Design and Analysis of Skewed-Distribution Scan Chain Partition for Improved Test Data Compression,” in Proc. IEEE International Symposium on Circuits and Systems, pp. 2641-2644, May 2008.
[13] K. S.-M. Li and J.-Y. Huang, “Interconnect-Driven Layout-Aware Multiple Scan Tree Synthesis for Test Time, Data Compression and Routing Optimization,” in Proc. 17th IEEE Asian Test Symposium, pp. 63-68, November 2008.
[14] Y.-W. Yang and K. S.-M. Li, “Temperature-Aware Dynamic Frequency and Voltage Scaling for Reliability and Yield Enhancement,” in Proc. 14th ACM/IEEE Asia and South Pacific Design Automation Conf., pp. 49-54, January 2009.
[15] S.-J. Wang, S.-J. Huang and K. S.-M. Li, “Static and Dynamic Test Power Reduction in Scan-Based Testing,” in Proc. IEEE International Symposium on VLSI Design, Automation and Test, pp. 56-59, April 2009.
[16] K. S.-M. Li, M.-H. Hsieh and S.-J. Wang, “Level Converting Scan Flip-Flops,” in Proc. IEEE International Symposium on Circuits and Systems, pp. 2505-2508, May 2009.
[17] K.-L. Fu, S.-J. Wang and K. S.-M. Li, “Low Peak Power ATPG for n-Detection Test,” in Proc. IEEE International Symposium on Circuits and Systems, pp. 1993-1996, May 2009.
[18] K. S.-M. Li, Y.-C. Hung and J.-Y. Huang, “Multiple Scan Trees Synthesis for Test Time/Data and Routing Length Reduction under Output Constraint,” in Proc. 18th IEEE Asian Test Symposium, pp. 231-236, November 2009.
[19] K. S.-M. Li, Y.-Y. Liao, Y.-W. Liu and J.-Y. Huang, “IEEE 1500 Compatible Interconnect Test with Maximal Test Concurrency,” in Proc. 18th IEEE Asian Test Symposium, pp. 269-274, November 2009.
[20] C.-C. Wang, K. S.-M. Li and S.-J. Wang, “A 1.8 V to 3.3 V Level-Converting Flip-Flop Design for Multiple Power Supply Systems,” in Proc. IEEE International Symposium on Integrated Circuits, pp. 61-64, December 2009.
[21] C.-Y. Pai and K. S.-M. Li, “Maximal Resilience for Reliability Enhancement in Interconnect Structure,” in Proc. 15th Workshop on Synthesis and System Integration of Mixed Information Technologies, pp. 296 - 301, October 2010.
[22] C.-Y. Pai and K. S.-M. Li, “Maximal Resilience for Reliability and Yield Enhancement in Interconnect Structure,” in Proc. 19th IEEE Asian Test Symposium, pp. 261-266, December 2010.
[23] K. S.-M. Li, S.-Y. Chen, L.-B. Chen and R.-T. Gu, “A Fast Custom Network Topology Generation with Floorplanning for NoC-based Systems,” in Proc. IEEE International Conference on Integrated Circuits Design and Technology, pp. 1-4, May 2011.
[24] Y.-X. Zheng, P.-P. Kan, L.-B. Chen, K.-Y. Hsieh, B.-C. Cheng and K. S.-M. Li , “Fault Tolerant Application-Specific NoC Topology Synthesis for Three-Dimensional Integrated Circuits,” in Proc. 24th IEEE International SoC Conference, pp. 296-301, September 2011.
[25] K.-Y. Hsieh, B.-C. Cheng, R.-T. Gu and K. S.-M. Li, “Fault-Tolerant Mesh for 3D Network on Chip,” in Proc. 6th IEEE International Microsystems, Packaging, Assembly and Circuits Technology conference, pp. 214-217, October 2011.
[26] C.-Y. Pai, R.-T. Gu, L.-B. Chen, B.-C. Chen and K. S.-M. Li, “A Unified Interconnects Testing Scheme for 3D Integrated Circuits,” in Proc. 20th IEEE Asian Test Symposium, pp. 195-200, November 2011.
[27] S.-J. Wang, H.-H. Hsu and K. S.-M. Li, “Low-Power Delay Test Architecture for Pre-Bond Test,” in Proc. IEEE International Symposium on Circuits and Systems, pp. 2321-2324, May 2012.
[28] B.-C. Cheng, K. S.-M. Li, and S. -J. Wang, “De Bruijn Graph-Based Communication Modeling for Fault Tolerance in Smart Grids,” in Proc. IEEE Asia Pacific Conference on Circuits and Systems Proceedings, pp. 623-626, December 2012.
[29] M.-K. Chiang and K. S.-M. Li, “Intelligent Home Management in the Smart Grids,” in Proc. IEEE Asia Pacific Conference on Circuits and Systems Proceedings, pp. 567-570, December 2012.
[30] R.-T. Gu, C.-Y. Ho, K. S.-M. Li, Y.-C. Ho, L.-B. Chen, K.-Y. Hsieh, J.-J Huang, B.-C. Cheng, S.-J. Wang and Z.-H. Gao, “A Layout-Aware Test Methodology for Silicon Interposer in 3D System-in-a-Package,” in Proc. IEEE International Symposium on Next-Generation Electronics, pp. 41-44, February 2013.
[31] Y. Ho, K. S.-M. Li, “A 0.3 V Low-power Temperature-insensitive Ring Oscillator in 90 nm CMOS Process,” in Proc. IEEE International Symposium on VLSI Design, Automation & Test, pp. 161-164, April 2013.
[32] S.-J. Wang, Y.-S. Chen and K. S.-M. Li, “Low-Cost Testing of TSVs in 3D Stacks with Pre-bond Testable Dies, ” in Proc. IEEE International Symposium on VLSI Design, Automation & Test, pp. 366-369, April 2013.
[33] S.-J. Wang, C.-H Lin and K. S.-M. Li, “Synthesis of 3D Clock Tree with Pre-bond Testability,” in Proc. IEEE International Symposium on Circuits and Systems, pp. 2654-2657, May 2013.
[34] K. S.-M. Li, C.-Y. Ho, S.-J. Wang, R.-T. Gu, J.-J. Huang, B.-C. Cheng and Y.-C. Ho, “A Layout-Aware Test Methodology for Silicon Interposer in System-in-a-Package,” in Proc. 22nd IEEE Asian Test Symposium, pp. 159-166, November 2013.
[35] Y.-C. Ho, K. S.-M. Li and S.-J. Wang, “Leakage Monitoring Technique in Near-threshold Systems with a Time-based Bootstrapped Ring Oscillator,” in Proc. 22nd IEEE Asian Test Symposium, pp. 91-96, November 2013.
[36] K.-Y. Hsieh, L.-B. Chen, and K. S.-M. Li, “A Timing-Aware Unified Methodology for Small Delay Defects Testing,” in Proc. 2014 IEEE 3rd International Symposium on Next-Generation Electronics, May 2014.
[37] S.-J. Wang, T.-H. Tzeng and K. S.-M. Li, “Fast and Accurate Statistical Static Timing Analysis,” in Proc. IEEE International Symposium on Circuits and Systems, pp. 2555-2558, Jun 2014.
[38] S.-J. Wang, C.-W. Kao and K. S.-M. Li, “Improving Output Compaction Efficiency with High Observability Scan Chains,” in Proc. 23nd IEEE Asian Test Symposium, pp. 324-329, Nov. 2014.
[39] K. S.-M. Li, S.-J. Wang, J.-L. Wu, C.-Y. Ho, Y. Ho, R.-T. Gu and B.-C. Cheng, “Optimized Pre-bond Test Methodology for Silicon Interposer Testing,” in Proc. 23nd IEEE Asian Test Symposium, pp.13-18, Nov. 2014.
[40] H.-C. Chen, C.-R. Wu, K. S.-M. Li, K.-J. Lee, “A Breakpoint-Based Silicon Debug Technique with Cycle-Granularity for Handshake-Based SoC,” in Proc. 15th IEEE Design, Automation & Test in Europe, pp.9-13, Mar. 2015, Grenoble, France.
[41] S.-J. Wang, C.-W. Kao and K. S.-M. Li, “High Observability Scan Chains with Improving Output Compaction Efficiency,” in Proc. 19th Workshop on Synthesis and System Integration of Mixed Integration of Mixed Information Technologies, pp.171-176, Mar. 2015.
[42] K. S.-M. Li, S.-J. Wang, X.-Y. Li, R.-T. Gu, B.-C. Cheng, “Pre-bond Interposer Test Methodology for System in Package,” in Proc. 19th Workshop on Synthesis and System Integration of Mixed Integration of Mixed Information Technologies, pp.151-156, Mar. 2015.
[43] J.-D. Li, S.-J. Wang, K. S.-M. Li and T.-Y. Ho, “Congestion-and Timing-Driven Droplet Routing for Pin-Constrained Paper-Based Microfluidic Biochips,” in Proc. 21th Asia and South Pacific Design Automation Conference, pp.593-598, Jan. 2016.
[44] J.-D. Li, S.-J. Wang, K.S.-M. Li and T.-Y. Ho, “Test and Diagnosis of Paper-Based Microfluidic Biochips,” in Proc. 34th IEEE VLSI Test Symposium, pp.1-6, 2016.
[45] S.-J. Wang, T.-J. Choi and K. S.-M Li, “Side-Channel Attack on Flipped Scan Chains,” in proc. 25th IEEE Asian Test Symposium, pp.67-72, Nov. 2016.
[46] S.-J. Wang, J.-Y. Wei, S.-H. Huang and K. S.-M. Li, “Test Generation for Combinational Hardware Trojans,” in proc. IEEE Asian Hardware Oriented Security and Trust Symposium, pp.1-6, 2016.
[47] K. S.-M. Li, et. al., “Internet of Things Security and Challenges,” in Proc. IEEE China Semiconductor Technology International Conference, pp. 175-178, March 2017.
[48] S.-J. Wang, K.-T. Yeh and K. S.-M. Li, “Exploiting Distribution of Unknown Values in Test Responses to Optimize Test Output Compactors,” in Proc. IEEE China Semiconductor Technology International Conference, March 2017.
[49] J.-D. Li, S.-J. Wang, K. S.-M. Li and T.-Y. Ho, “Design-for-Testability for Paper-based Digital Microfluidic Biochips,” in Proc. IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, pp.1-1, Oct. 2017.
[50] S.-J. Wang, H.-H. Chen, C.-H. Lien and K. S.-M. Li, “Testing Clock Distribution Networks,” in Proc. IEEE 26th Asian Test Symposium, pp. 163-168, 2017.
[51] J.-L. Wu, K. S.-M. Li, S.-J. Wang and T.-Y. Ho, “SOLAR: Simultaneous Optimization of Control-Layer Pins Placement and Channel Routing in Flow-Based Microfluidic Biochips,” in proc. IEEE International Symposium on VLSI Design, Automation and Test, pp. 1-4, 2018.
[52] S.-J. Wang, C.-H. Lien and K. S.-M. Li, “Register PUF with No Power-Up Restrictions,” in Proc. IEEE International Symposium on Circuits and Systems, pp. 1-5, May 2018.
[53] K. S.-M. Li, R.-Y. Chen, X.-H. Jiang, S.-J. Wang, S.-W. Lee, C.-L. Hsu and C.-T. Sun, “DAN: Anomaly Detection in Fully Automatic Smart Manufacturing Systems Using Hybrid DWT-Based Predictive Time-Series Analytics,” in Proc. IEEE International Test Conference in Asia, pp.1-5, August 2018.
[54] J.-D. Li, S.-J. Wang, K. S.-M. Li and T.Y- Ho, “Digital Rights Management for Paper-Based Microfluidic Biochips,” in Proc. IEEE 27th Asian Test Symposium, pp.1-5, October 2018.
[55] S.-J. Wang, K.-Y Hsu, C.-Y. Liu and K. S.-M. Li, "Combinational Hardware Trojan Construction and Layout-Aware Test Generation," in Proc. IEEE 27th Asian Test Symposium, pp.1-5, October 2018.

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III. Domestic Conferences:
[1] K. S.-M. Li, Y.-H. Cherng and Y.-W. Chang, “Noise-Aware Buffer Planning for Interconnect-Driven Floorplanning,” in Proc. 13th VLSI Design/CAD Symposium, August 2002.
[2] K. S.-M. Li, C.-L. Lee, C. Su and J.-E Chen, “A Unified Approach to Detecting Crosstalk Faults of Interconnects in Deep Sub-micron VLSI,” in Proc. 15th VLSI Design/CAD Symposium, August 2004.
[3] K. S.-M. Li, C.-L. Lee, C. Su, and J.-E Chen, “Oscillation Ring Based Interconnect Test Scheme for SOC,” in Proc. 15th VLSI Design/CAD Symposium, August 2004.
[4] K. S.-M. Li, C.-L. Lee, Y.-W. Chang, C. Su, and J.-E Chen, “IEEE Standard 1500 Compatible Interconnect Diagnosis for Delay and Crosstalk Faults,” in Proc. 16th VLSI Design/CAD Symposium, August 2005.
[5] K. S.-M. Li, C.-L. Lee, Y.-W. Chang, C. Su and J.-E Chen, “Multilevel Full-Chip Routing with Testability and Yield Enhancement,” in Proc. 16th VLSI Design/CAD Symposium, August 2005
[6] K.-L. Peng, S.-J. Wang and K. S.-M. Li, “Layout-Aware Scan Chain Reorder for Skewed-Load Transition Test Coverage,” in Proc. 17th VLSI Design/CAD Symposium, August 2006.
[7] X.-L. Li, S.-J. Wang and K. S.-M. Li, “Layout-Aware Multi-Layer Multi-Level Scan Tree Synthesis,” in Proc. 17th VLSI Design/CAD Symposium, August 2006.
[8] S.-J. Wang, P.-C. Tsai, H.-M. Weng and K. S.-M. Li, “Test Data and Test Time Reduction for LOS Transition Test in Multi-Mode Segmented Scan Architecture,” in Proc. 18th VLSI Design/CAD Symposium, August 2007.
[9] S.-J. Wang, S.-C. Chen and K. S.-M. Li, “Enhancing Compression Efficiency with Skewed-Probability Scan Chains,” in Proc. 18th VLSI Design/CAD Symposium, August 2007.
[10] J.-Y. Huang and K. S.-M. Li, “Interconnect-Driven Multiple Scan Tree Synthesis for Both Test Compression and Test Application Time,” in Proc. 1st VLSI Test Technology Workshop, July 2007.
[11] Y.-W. Liu, J.-Y. Huang and K. S.-M. Li, “IEEE 1500 Compatible Interconnect Oscillation Parallel Test,” in Proc. 2nd VLSI Test Technology Workshop, July 2008.
[12] K.-L. Fu, S.-J. Wang and K. S.-M. Li, “Low Peak Power ATPG and Test Compaction for n-Detection Test,” in Proc. 19th VLSI Design/CAD Symposium, August 2008.
[13] S.-J. Wang, S.-J. Huang and K. S.-M. Li, “Static and Dynamic Test Power Reduction in Scan-Based Testing by Input Vector Control,” in Proc. 19th VLSI Design/CAD Symposium, August 2008.
[14] K. S.-M. Li, Y.-C. Hung and J.-Y. Huang, “Multiple Scan Trees Synthesis for Test Time/Data and Routing Length Reduction under Output Constraint,” in Proc. 3rd VLSI Test Technology Workshop, July 2009.
[15] K. S.-M. Li, Y.-Y. Liao, Y.-W. Liu and J.-Y. Huang, “IEEE 1500 Compatible Multilevel Maximal Concurrent Interconnect Test,” in Proc. 3rd VLSI Test Technology Workshop, July 2009.
[16] S.-Y. Chen and K. S.-M. Li, “Fast Custom Co-Floorplanning NoC Generation,” in Proc. 21th VLSI Design/CAD Symposium, August 2010.
[17] C.-Y. Pai and K. S.-M. Li, “Maximal Resilience for Reliability and Yield Enhancement in interconnect Structure,” in Proc. 4th VLSI Test Technology Workshop, August 2010.
[18] C.-Y. Pai, L.-B. Chen, B.-C. Cheng, J.-C. Chen, K. S.-M. Li and J.-J. Chen, “Oscillation Ring Test Scheme for Horizontal/Vertical Interconnects in 3D Integrated Circuits,” in Proc. 5th VLSI Test Technology Workshop, July 2011.
[19] B.-C. Cheng, T.-T. Ku, S.-H. Yang, C.-S. Chen, K.-C. Kuo, C.-C. Wang, K-.Y. Hsieh, L.-B. Chen, and K. S.-M. Li, “Fault-Tolerant Communication Modeling for Smart Grid Electric Power Systems,” in Proc. 5th VLSI Test Technology Workshop, July 2011.
[20] Y.-X. Zheng, L.-B. Chen, K.-Y. Hsieh and K. S.-M. Li, “Application-Specific NoC Topology Synthesis with Fault Tolerance for 3D ICs,” in Proc. 22th VLSI Design/CAD Symposium, August 2011.
[21] S.-J. Wang, Y. -S Chen and K. S.-M. Li, “Low-Cost Testing of TSVs in 3D Stacks with Pre-bond Testable Dies,” in Proc. 6nd VLSI Test Technology Workshop, July 2012.
[22] S.-J. Wang, H.-H Hsu and K. S.-M. Li, “Delay Test Scheme for Low-Power Pre-Bond,” in Proc. 23th VLSI Design/CAD Symposium, August 2012.
[23] C.-Y. Ho, S.-J. Wang, R.-T. Gu, J.-J. Huang, B.-C. Cheng, Y.-C. Ho and K. S.-M. Li, “A Layout-Aware Test Methodology for Silicon Interposer in System-in-a-Package,” in Proc. 7th VLSI Test Technology Workshop, July 2013.
[24] W.-C. Lien, K.-J. Lee, T.-Y. Hsieh, K. C. and K. S.-M. Li, “An Internal-Response-Based LFSR Reseeding Technique,” in Proc. 24th VLSI Design/CAD Symposium, August 2013.
[25] C.-L. Wu, C.-Y. Ho, S.-Y. Wang and K. S.-M. Li, “Interposer Test for Open Fault,” in Proc. 8th VLSI Test Technology Workshop, July 2014.
[26] C.-L. Wu, C.-Y. Ho, S.-Y. Wang and K. S.-M. Li, “Interposer Test for Short Fault,” in Proc. 25th VLSI Design/CAD Symposium, August 2014.
[27] J.-D. Li, S.-J. Wang, T.-Y. Ho and K. S.-M. Li, “Test and Diagnosis of Paper-Based Microfluidic Biochips,” in Proc. 9th VLSI Test Technology Workshop, July 2015.
[28] H.-C. Chen and K. S.-M. Li, “Big Data Analysis and Prediction by Machine Learning in High Frequency Trading Application,” in Proc. Cloud Computing and Big Data Analysis Conference, 2016. (Best Paper Award)
[29] S.-J. Wang, J.-Y. Wei, S.-H. Huang and K. S.-M. Li, “Test Generation for Combinational Hardware Trojans,” in Proc. 10th VLSI Test Technology Workshop, July 2016.
[30] J.-D. Li, S.-J. Wang, K. S.-M. Li and T.-Y. Ho, “Conductive Wire Routing for Pin-Constrained Paper-Based Microfluidic Biochips,” in Proc. 27th VLSI Design/CAD Symposium, 2016.
[31] J.-L. Wu, T.-Y Ho, K. S.-M. Li and S.-J. Wang, “Flow-based Microfluidic Synthesis Consideration Skew,” in Proc. 27th VLSI Design/CAD Symposium, 2016.
[32] J.-D. Li, S.-J. Wang, K. S.-M. Li and T.-Y. Ho, “A Diagnosis Method with Fault Tolerance for Paper-Based Microfluidic Biochips,” in Proc. 27th VLSI Design/CAD Symposium, 2016.
[33] J.-D. Li, S.-J. Wang, K. S.-M. Li and T.-Y. Ho, “Detection for Stealthy Combinational Hardware Trojans,” in Proc. 11th VLSI Test Technology Workshop, July 2017.
[34] S.-J. Wang, J.-Y. Wei, S.-H. Huang and K. S.-M. Li, “Digital Rights Management for Paper-Based Microfluidic Biochips,” in Proc. 11th VLSI Test Technology Workshop, July 2017.
[35] J.-D. Li, S.-J. Wang, K. S.-M. Li and T.-Y. Ho, “Co-Placement Optimization of Cyber-Physical Digital Microfluidic Biochips for Testing,” in Proc. 11th VLSI Test Technology Workshop, July 2017.
[36] S.-J. Wang, H.-H. Chen, C.-H. Lien and K. S.-M. Li, “Testing Clock Distribution Networks,” in Proc. 11th VLSI Test Technology Workshop, July 2017.
[37] S.-J. Wang, C.-H. Lien, Y.-Y. Li and K. S.-M. Li, “Scan PUF with On-Line Evaluation,” in Proc. 12th VLSI Test Technology Workshop, July 2018.
[38] J.-D. Li, S.-J. Wang, K. S.-M. Li and T.-Y. Ho, “Design-for-Reliability for Paper-Based Digital Microfluidic Biochips,” in Proc. 12th VLSI Test Technology Workshop, July 2018.
[39] J.-L. Wu, K. S.-M. Li, J.-D. Li, S.-J. Wang and T.-Y. Ho, “SOLAR: Skew-Consideration and Optimization of Control-Layer Pins Placement and Channel Routing in Reliable Flow-Based Microfluidic Biochips,” in Proc. 12th VLSI Test Technology Workshop, July 2018.

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Edited by Ian Li, 2018/07/13, E-mail: g105056134@mail.nchu.edu.tw
Checked by Zih-Yun Peng, 2011/08/20, E-mail: j98224@hotmail.com